Chips of handheld devices have strict requirements on battery life and power consumption, and the dynamic voltage frequency scaling (DVFS) technology can effectively reduce dynamic power consumption by dynamically scaling the working frequency (F) and working voltage (V) according to the real-time load demand of the operating system of the handheld device. At present, one of the important technical problems in the application of the DVFS technology is how to ensure normal operation of peripheral components on the bus during bus dynamic frequency scaling (DFS).
In the implementation of the present invention, the inventor finds that, numerous peripheral components have various constraints on the bus clock, but the clock constraints cannot be satisfied during dynamic variation of the bus clock. In order to ensure normal operation of the peripheral components on the bus during the bus DFS, in the prior art, a separated structure of clock domains is adopted, which will increase the number of the clock domains, thus increasing the complexity of the implementation of the system; or complex modifications are made to the peripheral components, so as to adapt the peripheral components to a variable-frequency bus, but such a solution is complex, because the modification to each peripheral component needs to be made according to the specific conditions. In view of the above, the existing technical solutions are complex to implement, and thus the application of DVFS is limited.